As semiconductor devices continue to scale downwards, e.g., shrink, the desired spacing between features (i.e., the pitch) also becomes smaller. To this end, in the smaller technology nodes, devices become more vulnerable to external stress. In this way, it becomes ever more difficult to fabricate devices with certain features to guarantee a robust chip due to critical dimension (CD) scaling and process capabilities, as well as materials that are used to fabricate such structures. As the semiconductor market comes to automotive, industrial and medical applications, robust chips are required to compose a safe electronic system.
As an example, electrostatic discharge (ESD) events can cause issues for a transceiver interface in certain applications, e.g., automotive applications. Specifically, Local Interconnect Network (LIN) and Controller Area Network (CAN) bus interfaces can require a relatively high robustness and an area-efficient ESD protection to meet precise standards, e.g., IEC 61000-4-2 and ISO10605, amongst other examples. However, some present ESD protection devices have a limited failure current, which leads to a lack of robustness, and a low holding voltage, which can cause a latch-up issue, and also a relatively too high trigger voltage to provide an effective protection capability. Therefore, a high performance ESD protection device with a relatively high failure current, a high holding voltage and a reasonable trigger voltage is necessary to meet such application.